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indexed addressing - translation to russian

ASPECT OF THE INSTRUCTION SET ARCHITECTURE IN MOST CENTRAL PROCESSING UNIT DESIGNS

Addressing modes; Indirect word; Address mode; Indirect address; Absolute coding; Absolute and relative coding; Indexed addressing; Indirect addressing; Relative coding; Effective address; Load Effective Address; Push Effective Address; Indirection bit; Indirection (computing); Special addressing modes for implementation of stacks; Conditional execution; Register indirect; Direct addressing; Address modes; Direct-addressing; Direct address (computing)

indexed addressing

общая лексика

индексная адресация

способ адресации, используемый в системах команд большинства процессоров, при котором исполнительный адрес равен сумме содержимого индексного и сегментного (базового) регистров, либо как сумма смещения, содержащегося в команде, и значения, находящегося в регистре

absolute coding

общая лексика

программирование в машинных кодах

популярный на первых ЭВМ, но практически вышедший из употребления метод программирования с использованием машинных команд и абсолютных адресов. Такая программа может непосредственно исполняться процессором без предварительной трансляции и компоновки. Может применяться в редких случаях при отладке встроенных систем на простых микропроцессорах

Смотрите также

absolute address; absolute code; machine code

effective address

общая лексика

исполнительный адрес

адрес ОЗУ или ПЗУ, вычисленный при исполнении программы в соответствии с указанным в команде способом адресации

синоним

EA

Смотрите также

address register; logical address; relative address

Definition

indirect address

<processor> An addressing mode found in many processors' instruction sets where the instruction contains the address of a memory location which contains the address of the operand (the "effective address") or specifies a register which contains the effective address. In the first case (indirection via memory), accessing the operand requires two memory accesses - one to fetch the effective address and another to read or write the actual operand. Register indirect addressing requires only one memory access. An indirect address may be indicated in assembly language by an operand in parentheses, e.g. in Motorola 68000 assembly MOV D0,(A0) writes the contents of register D0 to the location pointed to by the address in register A0. Indirect addressing is often combined with pre- or post- increment or decrement addressing, allowing the address of the operand to be increased or decreased by one (or some specified number) either before or after using it. (1994-11-07)

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Wikipedia

Addressing mode

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

In computer programming, addressing modes are primarily of interest to those who write in assembly languages and to compiler writers. For a related concept see orthogonal instruction set which deals with the ability of any instruction to use any addressing mode.

https://en.wikipedia.org/wiki/Addressing mode

What is the Russian for indexed addressing? Translation of &#39indexed addressing&#39 to Russian